Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein a gate contact or electrode is energized to create an electric field in a channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel. A gate dielectric or gate oxide is formed over the channel, and a gate electrode or gate contact is formed over the gate dielectric. The gate dielectric and gate electrode layers are then patterned to form a gate structure overlying the channel region of the substrate. Complementary MOS (CMOS) devices have become widely used in the semiconductor industry, wherein both n-channel and p-channel (NMOS and PMOS) transistors are used to fabricate logic and other circuitry.
Continuing trends in semiconductor product manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and power consumption. MOS transistor performance may be improved by reducing the distance between the source and the drain regions under the gate electrode of the device, known as the gate or channel length, and by reducing the thickness of the layer of gate oxide that is formed over the semiconductor surface. However, scaled MOS transistors suffer from so-called short channel effects, wherein simply reducing the transistor channel length may degrade performance. Short channel effects include increased off-state (e.g., leakage) current, punch-through current, carrier drift velocity saturation, threshold voltage shifts, degraded subthreshold slope, and degraded output current. In addition, drain voltages may have a greater impact on channel performance in short channel devices, wherein the barrier for electron injection from the source to the drain may be decreased, a situation sometimes referred to as drain induced barrier lowering (DIBL).
Scaled MOS transistors may also suffer from channel hot carrier effects. For example, during saturation operation of a MOS transistor, electric fields are established near the lateral junction of the drain and channel regions. These fields causes channel electrons to gain kinetic energy and become “hot”. Some of these hot electrons traveling to the drain are injected into the thin gate dielectric proximate the drain junction. The injected hot carriers lead to undesired degradation of the MOS device operating parameters, such as a shift in threshold voltage, changed transconductance, changed drive current/drain current exchange, and device instability. To combat short channel and channel hot carrier effects, drain extension regions are commonly formed in the substrate, which are variously referred to as double diffused drains (DDD), lightly doped drains (LDD), moderately doped drains (MDD), and heavily doped drains (HDD). These relatively shallow drain extension regions absorb some of the potential into the drain and away from the drain/channel interface, thereby reducing channel hot carriers and the adverse performance degradation associated therewith.
While such ultra-shallow drain extensions help to alleviate short channel effects, these structures may cause high series resistance and parasitic capacitance that offset the performance gains achieved through scaling. Scaled semiconductor devices have accordingly been introduced wherein selective epitaxial growth (SEG) is employed to form an epitaxial layer in an elevated source/drain (ESD) structure. Elevating the source/drain regions operates to reduce the series resistance of the transistor, suppress short channel effects, counteract parasitic bipolar transistor action, and also provides extra silicon material for consumption during subsequent silicidation to form source/drain contacts.
In other devices, recesses are formed in the source/drain regions of the substrate, which are then filled with deposited epitaxial silicon, wherein the epitaxial growth may be continued to elevate the source/drains above the original substrate level. Providing deposited silicon may further enhance transistor device performance by inducing strain in the channel substrate material, thereby increasing carrier mobility therein. In this regard, carrier (e.g., hole) mobility in PMOS devices has benefited from introduction of uniaxial compressive strain along the direction of the channel by depositing silicon in recesses of the source/drain regions outlying the channel. For NMOS devices, electron mobility may be enhanced by a number of techniques, for example, by forming a tensile strained pre-metal dielectric (PMD) material over the transistor to create a tensile strain in the channel.
Thus, selective epitaxial growth techniques advantageously reduce short channel effects and may also be used to improve carrier mobility in scaled MOS transistors. However, selective deposition of silicon material to fill source/drain recesses and/or to elevate source/drain structures may result in deposition or growth over the gate contact. In particular, where the gate contact material is polysilicon and the polysilicon is unprotected, selective epitaxial growth processes result in deposition of single crystal silicon on the silicon source/drain regions as well as formation of polycrystalline silicon material (e.g., polysilicon) on the polysilicon gate. The deposition or growth on the polysilicon gate proceeds both vertically as well as laterally, wherein the deposited polysilicon extends outward over portions of the gate sidewall spacers. This phenomena is sometimes referred to as poly mushrooming.
The lateral extension of the gate polysilicon reduces the poly-to-contact spacing in the device, thereby making manufacturing more difficult. The vertical extension of the gate polysilicon also adds to the height of the transistor gate, which may hinder efforts to provide dopants in the gate polysilicon near the gate dielectric interface, leading to poly depletion problems. Alternatively, the gate polysilicon can be initially made thinner than a desired final gate electrode thickness, but this does not help poly-to-contact spacing problems and may make controlling the final thickness more difficult, particularly as the selective deposition provides three dimensional growth. Thus, there is a need for improved techniques for fabricating elevated and/or recessed source/drain MOS transistors to combat short channel effects in scaled devices, while avoiding or mitigating the adverse effects of gate poly mushrooming.